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What I know (including hearsay): (1) This documents the non-Deluxe Option Board, and the Deluxe Option Board is different. (2) I haven't tried wrangling any code around this as yet. Maybe someday, but frankly the Catweasel is higher on my copious free time list. (3) There are at least two versions of the non-Deluxe Option Board: a long card with three horizontal rows of several ICs, and a short card with three horizontal columns of several ICs. The short card has a "skirt" that prevents it being plugged into a 16-bit ISA slot, which is pretty weird for a card with a silkscreened copyright date of 1986.
The TRANSCOPY board has one input port and one output port. Both ports are accessed by the same address. The default port address is 6EF. Alternate port addresses of 66F, 76F, and 7EF are available by cutting one or both of the "bow ties" on the board. Reading and writing data to/from the drive is accomplished through use of DMA.
The input port is a single bit status port. Bit 7 of this port indicates the current state of the index signal from the drive. This is low for the duration of the index pulse (approx. 3 to 5 ms) and high otherwise.
The output port is an 8-bit control port defined as follows:
| Bit | Definition |
| 7 | CD1 |
| 6 | CD0 |
| 5 | COUNT2 |
| 4 | COUNT1 |
| 3 | COUNT0 |
| 2 | WTENBL |
| 1 | RDENBL |
| 0 | GO |
During reading, CD1 and CD0 are used to determine the data rate for the WS9216 (or UM8326) digital phase lock loop. CD1=0 and CD0=1 is used for reading standard 5 1/4" MFM disks.
During writing, CD1, CD0, COUNT2, COUNT1, and COUNT0 are used to determine the write clock divisor. The write clock frequency is equal to 16 MHz/divisor.
For writing standard 5 1/4" MFM disks, the following values are used:
| COUNT2 | CD1 | CD0 | COUNT1 | COUNT0 | DIVISOR | |
| 0 | 1 | 1 | 0 | 0 | 28 | 12% fast |
| 0 | 1 | 1 | 0 | 1 | 29 | 9% fast |
| 0 | 1 | 1 | 1 | 0 | 30 | 6% fast |
| 0 | 1 | 1 | 1 | 1 | 31 | 3% fast |
| 1 | 0 | 0 | 0 | 0 | 32 | nominal (center) frequency |
| 1 | 0 | 0 | 0 | 1 | 33 | 3% slow |
| 1 | 0 | 0 | 1 | 0 | 34 | 6% slow |
| 1 | 0 | 0 | 1 | 1 | 35 | 9% slow |
WTENBL is used to enable writing to the drive. The /WRITE GATE signal to the drive is active (low) whenever WTENBL is high.
RDENBL is used to enable reading from the drive.
GO is used to enable DMA activity to/from the board. The DMA channel used is jumper selectable for either channel 1 or 2.
Generally a track is read from leading edge of index to leading edge of index. Since a bit is read every 2 us, the usual track length is around 3100H bytes. Since tracks may be longer, a DMA count of 34FFH is typically used. No data separation or byte boundary synchronization is performed by the hardware. The raw bits off the track are read into the DMA buffer.
The read routine flowchart follows:
Head selection is accomplished by giving the NEC a READ ID command for the desired head, but not requesting the bytes from the result phase until later. The proper head will be selected until these result phase bytes are requested, which is done at the end (DESELECT HEAD).
The DMAGATE on the IBM controller must be turned off if DMA channel 2 is used, since the controller also uses this channel. A false disk interrupt is usually generated when DMAGATE is turned on or off because DMAGATE also controls the disk interrupt lines.
When setting up DMA, make sure that no attempt is made to cross a 64k page boundary.
Writing a track is very similar to reading. The write flowchart follows:
It is necessary to turn off WTENBL before allowing DMA to complete in order to avoide extraneous writing to the drive after index.
It is possible to write past index if it is desired to place the track splice at some other point on the track.